This invention relates to a serial data communication bus system for enabling data to be passed between individual autonomous components of a system, such as a control system.
For flight-critical aircraft control systems, it is considered to be crucial that a communication bus system should be deterministic, that is to say that packets of data from individual autonomous components of the control system are transmitted in a way which is predictable with respect to time. This could be achieved by adopting a master/slave bus architecture in which a master component requests each of the other components to transmit data in a predetermined sequence. This arrangement is, however, slow and deterministic operation without a bus-master is preferable.
A deterministic bus system has been proposed and is described in U.S. Pat. No. 4,199,663 and U.S. Pat. No. 4,471,481. This uses specifically designed hardware to impose a deterministic data transfer protocol in which individual autonomous components of the control system transmit in a predetermined order. As the number of aircraft control systems is relatively small, however, this specifically designed hardware is manufactured in very small quantities and is therefore expensive.
Various non-deterministic bus systems have been proposed for use in automotive and industrial applications. As such applications call for mass production techniques, the hardware required is relatively inexpensive.
The present invention is based upon the realisation that the hardware which is mass produced for automotive and industrial applications can be employed with relatively simple and inexpensive added hardware in a deterministic bus system suitable for use in aircraft control systems.
In accordance with the invention, there is provided a deterministic bus control for use in an autonomous component of a control system and comprising a conventional bus controller having means for inputting data to be transmitted and means for inputting transmit requests, a buffer for receiving and storing transmit requests from said autonomous component and a deterministic transmission scheduler connected to the bus for detection of the status thereof and to the transmit request buffer for causing transmit requests to be passed to the transmit request input means of the controller in accordance with a deterministic protocol imposed by the scheduler.
The conventional bus controller may be in the form of an integrated circuit intended for use in a CAN (controller area network). The scheduler is preferably arranged to impose the deterministic transmission protocol employed in ARINC 629 systems, such as that described in U.S. Pat. No. 4,471,481.